In designing an integrated circuit (IC) device, engineers or designers typically rely on computer design tools to help create an IC schematic or design, which can include a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the IC device in or on a semiconductor substrate, the IC device schematic must be translated into a physical representation or layout, which itself can then be transferred onto a semiconductor substrate. Computer aided design (CAD) tools, can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed IC device. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects and the like.
The software programs employed by the CAD systems to produce layout representations are typically structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, the design rules are determined by certain processing and design limitations based roughly on the patternability of layout designs. For example, design rules may define the space tolerance between devices or interconnect lines.
Once the layout of the circuit has been created, the next step to manufacturing the IC device is to transfer the layout onto a semiconductor substrate. Optical lithography or photolithography is a well-known process for transferring geometric shapes onto the surface on a semiconductor wafer. The photolithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor substrate or wafer. A reticle or mask having fully light non-transmissive opaque regions, which are often formed of chrome, and fully light transmissive clear regions, which are often formed of quartz, is then positioned over the photoresist coated wafer.
The mask is placed between a radiation or light source, which can produce light of a pre-selected wavelength (e.g., ultraviolet light) and geometry, and an optical lens system, which may form part of a stepper apparatus. When the light from the light source is directed onto the mask, the light is focused to generate a reduced mask image on the wafer, typically using the optical lens system, which may contain one or several lenses, filters, and/or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed or unexposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern, which defines the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
There is a pervasive trend in the art of IC design and fabrication to increase the density with which various structures are arranged and manufactured. For example, minimum line widths (often referred to as critical dimension (CD)), separations between lines, and pitch are becoming increasingly smaller. As the scale of designs and CDs continue to decrease, resolution enhancement techniques (RET) have been employed in lithographic processing in order to achieve sub-wavelength imaging. However, each specific RET has its own advantages and limitations. Depending upon the specific RET used, a given set of features within a layout can have its resolution improved or degraded. It is up to the lithographer and/or designer to determine an optimal combination. This is difficult, because of the interaction between various RETs, and time-consuming using conventional techniques. Typically, the illuminator/numerical aperture (NA)/reticle parameter space is not fully explored, which can affect overall manufacturability. This problem is magnified by the use of aggressive RET strategies, such as dipole illumination, quadrupole illumination, and alternating phase shift masks (PSM), which can result in higher layout-RET interaction.
Accordingly, a need exists in the art for an improved system and method for IC device design and manufacture.